1. Field of the Invention
The present invention generally relates to a lithographic process for printing small features, and more particularly, to a projection-type optical lithographic process taking advantage of double exposure and dual phase shift mask (PSM), which is capable of solving a phase conflict due to two close small features and avoiding the manufacture of a troublesome 45-degree trim mask. The two PSMs are disposed at the same position relative to the wafer in the double exposure processes without the need of rotation or any displacement.
2. Description of the Prior Art
Lithography processing, which is an essential technology when manufacturing conventional integrated circuits, is used for defining geometries, features, lines, or shapes onto a die or wafer. In the integrated circuit making processes, lithography plays an important role in limiting feature size. By using lithography, a circuit pattern can be precisely transferred onto a die or wafer. Typically, to implement the lithography, a designed pattern such as a circuit layout pattern or an ion doping layout pattern in accordance with a predetermined design rule is created on one or several mask in advance. The pattern on the mask is then transferred by light exposure, with a stepper and scanner, onto the wafer. In general, a photosensitive material, such as photoresist, is coated over a top surface of a die or wafer to selectively allow for the formation of the desired geometries, features, lines, or shapes.
One known method of lithography is optical lithography. The optical lithography process generally begins with the formation of a photoresist layer on the top surface of a semiconductor wafer. A mask having fully light non-transmissive opaque regions, which are usually formed of chrome, and fully light transmissive clear regions, which are usually formed of quartz, is then positioned over the aforementioned photoresist coated wafer. Light is then shone on the mask via a visible light source or a ultraviolet light source such as KrF laser (248 nm), ArF laser (193 nm), F2 laser (157 nm) or extreme UV. In almost all cases, the light is reduced and focused via an optical lens system, which contains one or several lenses, filters, and or mirrors. This light passes through the clear regions of the mask and exposes the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer coated with a photoresist layer exhibiting a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
Since the cutting edge non-optical lithography processing such as electron beam (e-beam) lithography is not mature yet and costly, a number of resolution enhancement techniques (RET) have therefore been proposed to promote the performance of the existing optical lithography, and, at the same time, elongate the life of lithography equipments thereof. By way of example, in U.S. Pat. No. 5,308,741 to Motorola, Inc., Kemp teaches a method using double exposure in combination with one phase shift mask and one displaced mask. In this method, a second mask is placed in a second position, which is displaced from the first position in an x direction, a y direction, and/or a rotational direction. However, this method involves extremely precise and sophisticated mask (or wafer) shifting and positioning to achieve the fine displacement in an x direction, a y direction, or a rotational direction. The design of a pattern layout on a mask is also complicated. Further, this method cannot solve a phase conflict due to two close small features.
In U.S. Pat. No. 5,858,580 to Numerical Technologies, Inc. issued in 1999 (hereinafter referred to as NTI patent), Wang et al. discloses a method for creating a phase shift mask and a trim mask for shrinking integrated circuit designs. One embodiment of this invention includes using a two-mask process. The first mask is a phase shift mask and the second mask is a single-phase trim mask. The phase shift mask primarily defines regions requiring phase shifting. The single-phase trim mask primarily defines regions not requiring phase shifting. However, this optical proximity correction (OPC) technique suffers from transmission imbalance occurred in phase shifted and non-phase shifted regions and other flaws caused by alt-PSM. Also, this method cannot overcome the above-mentioned phase conflict problem.
Please refer to FIG. 1. FIG. 1 is a schematic diagram demonstrating a part of a phase shift mask (PSM) layout 20 and a part of a trim mask layout 30, which are required for exposing a final pattern 10 including two small features arranged in close proximity on a photoresist layer. As shown in FIG. 1, the final pattern 10 includes a vertical fine line 101, a horizontal fine line 102, avertical fine line 104, and a horizontal fine line 103. The vertical fine line 101 is connected to the horizontal fine line 102 in an orthogonal manner, and the vertical fine line 104 is connected to the horizontal fine line 103 in an orthogonal manner. The line width of the vertical fine line 101, horizontal fine line 102, vertical fine line 104, and horizontal fine line 103 is assumed as D1, for example, D1 ranges from 0.1 to 0.25 micrometers, and the distance between the horizontal fine line 102 and the horizontal fine line 103 is assumed as D2, for example, D2 ranges from 0.2 to 2.5 micrometers. According to the NTI patent, to form a final pattern 10 as illustrated in FIG. 1 on a positive photoresist layer, it requires a phase shift mask (PSM) layout 20 and a trim mask layout 30. The PSM layout 20 includes a control chrome line 201, a control chrome line 202, a control chrome line 203, a control chrome line 204, and an opaque area 206. A phase contrast region consisting of a 0 degree phase clear area 210 adjacent to a 180 degree phase clear area 212 is provided to form the vertical fine line 101 image. A phase contrast region consisting of a 0 degree phase clear area 214 adjacent to a 180 degree phase clear area 212 is provided to form the vertical fine line 104 image. However, as specific indicated by numeral 250, the formation of the horizontal fine lines 102 and 103 is not possible since there is no phase contrast within the phase shifting area 212.
Please refer to FIG. 2. FIG. 2 is another prior art example according to NTI's OPC method, which is proposed in 2002. As shown in FIG. 2, to print a small feature pattern 40, a PSM layout 50 and a trim mask layout 60 are prepared in advance. In this case, the small feature pattern 40 includes a vertical fine line 401 and a horizontal fine line 402 connected to the vertical fine line 401 in an orthogonal manner. A PSM layout 50 and a trim mask layout 60 are required for generating pattern 40 on a positive photoresist layer (not shown). The PSM layout 50 includes a control chrome line 501, a control chrome line 502, 0 degree phase clear areas 505a and 505b, 180 degree phase clear areas 506a and 506b, and an opaque area 509. The horizontal fine line 402 can be generated on the photoresit layer through interference caused by a 180 degree phase contrast between the 0 degree phase clear area 505a (and 505b) and 180 degree phase clear area 506a. Likewise, the phase contrast between the 0 degree clear area 505a and 180 degree phase clear area 506b results in the vertical fine line 401. However, according to this method, an transition 45 degree angle small feature is inevitably created by the phase contrast between the 0 degree phase clear area 505b and 180 degree phase clear area 506b at the corner area as indicated by numeral 550, which has to be removed later on. To erase the 45-degree small feature, a trim mask 60 having a 45-degree small clear area (see the area indicated by numeral 650) corresponding the 45 degree small feature is required in a second exposure process. This trim mask having such 45-degree small clear area is difficult to manufacture and raises the cost of chip making.